(1) Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly relates to a method for fabricating a high-reliability semiconductor device, which can restrain variations in the threshold voltage of a p-channel type metal insulator semiconductor (MIS) transistor (p-type metal insulator semiconductor field effect transistor (MISFET)) and the lowering of the saturation drain current thereof when it is used over the long term.
(2) Description of Related Art
In recent years, refinement and increase in density of semiconductor integrated circuits have been advancing. Under the deep-submicron design rule, so-called dual gate structures are currently dominating in which n+ gate electrodes are used for n-type MISFETs of complementary metal insulator semiconductor (CMIS) transistors and p+ gate electrodes are used for p-type MISFETs thereof. However, in a CMIS large scaled integration (CMISLSI) having this dual gate structure, boron that has been introduced into a polycrystalline polysilicon film to form a p+ gate electrode for a p-type MISFET penetrates a gate insulating film in a later heat treatment step and diffuses also into a channel region of a p-type MISFET. This phenomenon called “boron penetration” easily occurs. It has been known that the occurrence of the phenomenon called boron penetration causes variations in transistor characteristics and a loss of the reliability of the gate insulating film.
A technique in which fluorine is implanted into a gate electrode to improve the reliability of a gate insulating film and prevent the transistor characteristics of a p-type MISFET from varying has been known as a technique for coping with the above problem (see, for example, Japanese Unexamined Patent Publication No. 11-163345).
A known fabrication method for a semiconductor device having a dual-gate structure will be described hereinafter with reference to the drawings.
FIGS. 7A through 7E are cross-sectional views showing process steps in the known fabrication method for a semiconductor device. The left side of each of FIGS. 7A through 7E shows a region Rn in which an n-type MISFET is to be formed (hereinafter, referred to as “n-type MISFET formation region Rn”), and the right side of each of FIGS. 7A through 7E shows a region Rp in which a p-type MISFET is to be formed (hereinafter, referred to as “p-type MISFET formation region Rp”).
First, in the process step shown in FIG. 7A of the known fabrication method for a semiconductor device, an n well 101A and a p well 101B are formed in parts of a silicon substrate 101 located in the p-type MISFET formation region Rp and the n-type MISFET formation region Rn, respectively. Thereafter, an isolation area 102 is formed in the silicon substrate 101 to surround active areas of the silicon substrate 101.
Next, in the process step shown in FIG. 7B, an oxide film 103 is formed on the silicon substrate 101, and then a non-doped polycrystalline silicon film 104 is formed on the oxide film 103.
Next, in the process step shown in FIG. 7C, the polycrystalline silicon film 104 and the oxide film 103 are patterned, thereby forming, on the active area of a part of the silicon substrate 101 located in the p-type MISFET formation region Rp, a gate electrode 104A and a gate insulating film 103A both for a p-type MISFET and forming, on the active area of a part of the silicon substrate 101 located in the n-type MISFET formation region Rn, a gate electrode 104B and a gate insulating film 103B both for an n-type MISFET.
Next, in the process step shown in FIG. 7D, fluorine ions 108 are implanted into the gate electrodes 104A and 104B and an exposed part of the silicon substrate 101 from the direction approximately perpendicular to the top surface of the silicon substrate 101 at an implantation energy of 10 keV and an implant dose of 2×1013 through 2×1015 ions/cm2.
Next, in the process step shown in FIG. 7E, sidewalls 105 made of a silicon oxide film are formed on the side surfaces of the gate electrodes 104A and 104B, respectively. Thereafter, n-type impurity diffusion layers 106 that will be source/drain regions of an n-type MISFET are formed in the n-type MISFET formation region Rn by implanting arsenic ions serving as an n-type impurity into a part of the silicon substrate 101 located in the n-type MISFET formation region Rn, and p-type impurity diffusion layers 107 that will be source/drain regions of a p-type MISFET are formed in the p-type MISFET formation region Rn by implanting boron ions serving as a p-type impurity into a part of the silicon substrate 101 located in the p-type MISFET formation region Rp. Thereafter, the entire substrate region is subjected to rapid heat treatment for activating the implanted impurity ions, thereby completing a p-type MISFET and an n-type MISFET. This rapid heat treatment allows fluorine ions to diffuse from the gate electrodes 104A and 104B into the gate insulating films 103A and 103B.
According to this fabrication method, since in a p-type MISFET fluorine is introduced into a gate insulating film 103A, this reduces the physical stress applied to a gate insulating film due to the difference in coefficient of thermal expansion between a gate electrode 104A and the gate insulating film 103A and improves the reliability of transistors. Furthermore, fluorine is introduced into a p+ gate electrode 104A at a dose of 2×1013 through 2×1015 ions/cm2, and the action of this fluorine can restrain boron introduced into the p+ gate electrode 104A from entering into the gate insulating film 103A and the semiconductor substrate 101 and prevent variations in transistor characteristics and deterioration of the reliability of transistors.
However, with the passage of time, the known fabrication method for a semiconductor device as shown in FIGS. 7A through 7E varies the threshold voltage and decreases the drain current.